oneAPI Developer Summit 2020

oneAPI Dev Summit 2020

Join us for the inaugural oneAPI Developer Summit focused on oneAPI and Data Parallel C++ for accelerated computing across xPU architectures (CPU, GPU, FPGA, and other accelerators). In this two-day virtual conference, you will hear from industry and academia speakers working on innovative cross-platform architecture solutions developed on oneAPI. Learn from fellow developers and connect with other innovators. Please join us, a self-sustained, vibrant community to support each other using oneAPI and Data Parallel C++.

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Day 1 - November 12th, 2020
Day 2 – November 13, 2020

Day 1 - November 12th, 2020

08:00 AM – 8:10 AM PDT

Introduction

Introduction

Sujata Tibrewala
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Sujata Tibrewala

Sujata Tibrewala is oneAPI Worldwide Developer Community manager at Intel who defines programs to enable developer community to use oneAPI. She is a co-chair for IEEE Edge Automation Platform Roadmap and is a frequent presenter at various IEEE and industry conferences. She has held positions of Director at Silicon Valley Engineering Council and TSC chair for Documentation Akraino. She is also a self taught artist who has exhibited at various venues in US and India including University of Illinois Chicago, Life Force Arts Center, Lalit Kala Academy etc.

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08:10 AM – 08:40 AM PDT

Keynote

oneAPI Vision for Heterogenous Compute

Joseph Curley
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Joseph Curley

Joseph (Joe) Curley serves Intel Corporation as Senior Director, oneAPI Products, Solutions & Ecosystem, SATG. His primary responsibilities include supporting the oneAPI industry initiative, product management of Intel’s oneAPI product implementation, and supporting the oneAPI developer ecosystem. Mr. Curley joined Intel Corporation in 2007, and has served in multiple other strategic planning, ecosystem development, and business leadership roles. Prior to joining Intel, Joe worked at Dell, Inc. leading the global workstation product line, the consumer and small business desktop product line, and in a series of engineering roles. He began his career at computer graphics pioneer Tseng Labs. 

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08:40 AM -09:20 AM PDT

Tech Talk 1

Building an Open AI & HPC Ecosystem

Andrew Richards
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Andrew Richards

CEO and co-founder of Codeplay, Andrew started his career writing video games in the days of 8-bit computers, progressing to become a lead games programmer at Eutechnyx™, where he wrote best-selling titles such as Pete Sampras Tennis and Total Drivin’. Codeplay has been producing compilers for games consoles, special-purpose processors and GPUs since then. As well as being CEO and Founder of Codeplay Software Ltd, Andrew is also the Chair of the Software working group of the HSA Foundation™ and former Chair of the SYCL™ for OpenCL™ sub-group of the Khronos® Group.  Andrew graduated from Cambridge University with a degree in Computer Science and Physics.

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09:20 AM -10:00 AM PDT

Tech Talk 2

Unifying and Accelerating Reverse Time Migration Programming with oneAPI

Ahmed Ayyad
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Ahmed Ayyad

Ahmed is a senior HPC software engineer and a member of Brightskies’ parallel programming team. He works on software benchmarking and code optimization/modernization of the company’s state of the art computational science and numerical analysis products. Ahmed’s work involved developing software optimized for different hardware architectures. Ahmed is part of the Brightskies team that is developing one of the earliest substantial products adopting the oneAPI and DPC++ technologies. Previously Ahmed worked at Valeo, developing automotive software solutions to multiple OEMs. Ahmed holds a B.Sc. in electrical engineering from Alexandria University. He has R&D experience in computer vision, machine learning/deep learning and software architecture.

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10:00 AM -10:10 AM PDT Break  
10:10 AM -10:50 AM PDT

Tech Talk 3

Boosting Productivity of Decision-making with oneAPI-based Heterogeneous Schedulers on SoCs

Denisa Constantinescu
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Denisa Constantinescu

Denisa Constantinescu

Denisa Constantinescu is a Ph.D. student in Mechatronics and a researcher in the Computer Architecture Department at the University of Malaga. She obtained a Master’s degree in Computer Engineering from the University of Malaga in 2017. She was a Research Visitor at the NUCAR Laboratory (Northeastern University, Boston, USA) in 2018. Her research interests are in parallel computing, robotics, intelligent control systems, optimization, and autonomous decision-making.

Professor Rafael Asenjo
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Professor Rafael Asenjo

Rafael Asenjo is a Professor of Computer Architecture at the University of Malaga, Spain. He obtained a PhD in Telecommunication Engineering in 1997 and was an Associate Professor at the Computer Architecture Department from 2001 to 2017. He was a Visiting Scholar at the University of Illinois in Urbana-Champaign (UIUC) in 1996 and 1997 and Visiting Research Associate in the same University in 1998. He was also a Research Visitor at IBM T.J. Watson in 2008 and at Cray Inc. in 2011. He has been using TBB since 2008 and over the last five years, he has focused on productively exploiting heterogeneous chips leveraging TBB as the orchestrating framework. In 2013 and 2014 he visited UIUC to work on CPU+GPU chips. In 2015 and 2016 he also started to research into CPU+FPGA chips while visiting U. of Bristol. He served as General Chair for ACM PPoPP’16 and as an Organization Committee member as well as a Program Committee member for several HPC related conferences (PPoPP, SC, PACT, IPDPS, HPCA, EuroPar, and SBAC-PAD). His research interests include heterogeneous programming models and architectures, parallelization of irregular codes and energy consumption. He has co-authored the latest book (open access) on Threading Building Blocks (TBB).

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10:50 AM -11:50 AM PDT

Lightning Talk

ATLAS Charged Particle Seed Finding with DPC++

Attila Krasznahorkay
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Attila Krasznahorkay

Attila Krasznahorkay is an Applied Physicist at CERN, having a PhD in Particle Physics. He currently convenes the Accelerator Software Forum of the ATLAS Experiment while working as a core software developer for the experiment, and convenes the Frameworks Working Group of the High Energy Physics Software Foundation (HSF). His work currently focuses on integrating accelerator aided calculations into the ATLAS Experiment’s simulation/reconstruction/analysis software and preparing the ATLAS Experiment’s software for the next data taking period of the Large Hadron Collider.

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10:50 AM -11:50 AM PDT

Lightning Talk

Making Banking Secure via Bio Metrics Application Built Using oneAPI with oneAPI Video Processing Library

Alessandro Faria
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Alessandro Faria

Alessandro was born in Bebedouro, state of Sao Paulo, Brazil. He is a speaker, researcher, founder of OITI TECHNOLOGIES. He has worked with technology since 1984, Linux since 1998, biometrics since 1999, facial biometrics since 2003, computer vision since 2005, and GPU since 2009. He is the inventor of CERTIFACE technology, Ambassador openSUSE Linux in Latin America., member OWASP since 2016, member Mozillians since 2017, official contributor OpenCV library since 2017, open source software contributor, and including maintainers librealsense in openSUSE Linux.

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10:50 AM -11:50 AM PDT

Lightning Talk

Gaining Support for Multiple Device by Migrating a CUDA Code to oneAPI -- Experiences with the Intel® DPC++ Compatibility Tool

Steffen Christgau
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Steffen Christgau

Steffen Christgau is a research associate in the Algorithms for Innovative Architectures research group of the Supercomputing Department at the Zuse Institute Berlin (ZIB). His current research interests are the efficient usage of persistent memory for HPC applications as well as their optimization for new hardware platforms with established and new programming environments. He received his Ph.D. as well as his M.Sc. degree in computer science from the University of Potsdam, Germany. While working at the Operating Systems and Distributed Systems group, his research focused on designing and optimizing MPI implementations for an experimental, non-cache-coherent many-core processor. Before he joined ZIB, he also worked in the industry on compiler implementations and robotic systems as well as a lecturer for parallel computing.

Marius Knaust
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Marius Knaust

Marius Knaust is a research associate in the Algorithms for Innovative Architectures research group of the Supercomputing Department at the Zuse Institute Berlin (ZIB). His current research interest is the application of FPGAs as HPC compute accelerators and improving the high-level synthesis workflow for it. He received his M.Sc. degree in software engineering from the Hasso Plattner Institute in Potsdam, Germany. Prior to joining ZIB, he worked at the division Microrobotics and Control Engineering of the University of Oldenburg and interned with the Mobile Research group of Yahoo Labs in the Silicon Valley.

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10:50 AM -11:50 AM PDT

Lightning Talk

Performance Portability with oneAPI: the CMS Physics Reconstruction Software

Laura Cappelli
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Laura Cappelli

Laura Cappelli is a computer science student at Alma Mater Studiorum – University of Bologna. Her studies span heterogeneous systems and parallel programming models, and her current research focuses on the use of SYCL from the Khronos Group and oneAPI from Intel for performance portability, and their application to physics reconstruction algorithms. In summer 2020, Laura participated to the CERN OpenLab programme, and is now working in collaboration with physicists from the CMS Experiment at CERN. She will defend her master’s thesis on “Performance portability of physics reconstruction algorithms on heterogeneous systems using the SYCL abstraction programming model” in early 2021.

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11:50 AM -12:10 PM PDT Lunch and Fun Activities  
12:10 PM – 12:50 PM PDT

Tech Talk 4

Optimizing Computer Aided COVID-19 Drug Design Tools with oneAPI

Ho Leung Ng
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Ho Leung Ng

Ho Leung Ng is an Associate Professor of Biochemistry & Biophysics at Kansas State University. His primary research interests include protein crystallography, structure-based drug design for cancer and immunology, computational chemistry, applications of machine learning to computational chemistry and drug design, immuno-oncology, protein kinases, estrogen pharmacology, GPCRs, hormone receptors, malaria, fluorescent proteins, and bio photonics. He is the founder of OpenSourceCOVID19 (www.opensourcecovid19.org).

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12:50 PM – 01:30 PM PDT

Tech Talk 5

Adopting oneAPI Into the NAMD Molecular Dynamics Application

David Hardy
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David Hardy

David Hardy is a senior research programmer at the University of Illinois at Urbana-Champaign. He leads the development of NAMD and was part of the research effort awarded in 2020 the ACM Gordon Bell Special Prize for High Performance Computing-Based COVID-19 Research.

Tareq Malas
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Tareq Malas

Tareq joined Intel after his postdoctoral fellowship in Lawrence Berkeley National Laboratory under the NERSC Exascale Science Applications Program. He obtained his MS and Ph.D. degrees from King Abdullah University of Science and Technology (KAUST), in Saudi Arabia, advised by Prof. David Keyes in the Extreme Computing Research Center. His main areas of research are High Performance Computing in stencil computations and molecular dynamics simulations. He is interested in developing efficient high-performance computing algorithms on contemporary and future architectures for the most demanding applications. He likes to work near the CPU, as he did his Stencil code generation project in performing efficient vectorization in the CPU of the PowerPC 450 processor of the Blue Gene/P supercomputer. He worked on developing novel cache blocking techniques for reducing the data movement in the processor’s memory hierarchy, allowing the use of cache blocks that can efficiency span multiple cache domains. This work was developed in his Girih project for Intel® CPU. He is currently working on the performance optimizations of molecular dynamics simulations.

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01:30 PM – 01:40 PM PDT Break  
01:40 PM – 02:40 PM PDT

Panel

oneAPI spec & Industry Panel

Ronan Keryell
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Ronan Keryell

Ronan Keryell

Ronan Keryell is principal software engineer at Xilinx Research Labs. He works on SYCL C++-based programming models for heterogeneous system like FPGA and CGRA. He is the specification editor of the SYCL standard, member of the SYCL, SPIR & OpenCL standard committees from Khronos Group & ISO C++ committee. Ronan Keryell received his MSc in Electrical Engineering and PhD in Computer Science in 1992 from École Normale Supérieure of Paris & University of Paris Sud (France), on the design of a massively parallel RISC-based VLIW-SIMD graphics computer and its programming environment. He was co-founder of 3 start-ups, mainly in high-performance computing, was the technical lead of the Par4All automatic parallelizer at SILKAN, targeting OpenMP, CUDA & OpenCL from sequential C & Fortran. Before joining Xilinx, he worked at AMD on programming models for GPU.

Nevin Liber
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Nevin Liber

Nevin Liber is a computer scientist in the ALCF (Argonne Leadership Computing Facility) division of Argonne National Laboratory, where he works on the oneAPI/DPC++/SYCL backend for Kokkos for Aurora. He also represents Argonne on the SYCL and C++ Committees, the latter as Vice Chair of LEWGI/SG18.

Penporn Koanantakool
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Penporn Koanantakool

Penporn Koanantakool is a senior software engineer at Google. She leads TensorFlow’s performance optimization collaboration with Intel. Penporn holds a Ph.D. in computer science from the University of California, Berkeley, and a B.Eng. in computer engineering from Kasetsart University, Thailand.

Andrew Lumsdaine
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Andrew Lumsdaine

Andrew Lumsdaine

Computing (NIAC), Andrew wears at least two hats: Laboratory Fellow at Pacific Northwest National Laboratory and Affiliate Professor in the Paul G. Allen School of Computer Science and Engineering. As a dual-appointee between UW and PNNL Andrew also has the title of “UW-PNNL Distinguished Faculty Fellow.” By spanning a university and a national laboratory he has the opportunity to work on basic research questions and then reduce those results to practice. His primary research interest is High Performance Computing, interpreted broadly. Of particular interest throughout most of his career has been scalable graph algorithms. He has also had a side interest in computational photography, which turned out to be surprising fruitful.

Moderator:

Gergana Slavova
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Gergana Slavova

Gergana Slavova

Gergana has 14 years’ experience in High Performance Computing (HPC). For the majority of her career, she has focused on customer enabling, training, and consulting for distributed applications using the Message Passing Interface (MPI) and Intel’s development tools. Most recently, she’s participating in the oneAPI industry initiative that works on defining an open cross-vendor, cross-platform programming model for accelerators.

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08:00 AM – 8:10 AM PDT

Closing

Closing

Sujata Tibrewala
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Sujata Tibrewala

Sujata Tibrewala is oneAPI Worldwide Developer Community manager at Intel who defines programs to enable developer community to use oneAPI. She is a co-chair for IEEE Edge Automation Platform Roadmap and is a frequent presenter at various IEEE and industry conferences. She has held positions of Director at Silicon Valley Engineering Council and TSC chair for Documentation Akraino. She is also a self taught artist who has exhibited at various venues in US and India including University of Illinois Chicago, Life Force Arts Center, Lalit Kala Academy etc.

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02:50 PM – 03:50 PM PDT

Happy Hour

Virtual Happy Hour and Networking

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Day 2 – November 13, 2020

08:00 AM – 8:10 AM PDT

Introduction

Introduction

Sujata Tibrewala
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Sujata Tibrewala

Sujata Tibrewala is oneAPI Worldwide Developer Community manager at Intel who defines programs to enable developer community to use oneAPI. She is a co-chair for IEEE Edge Automation Platform Roadmap and is a frequent presenter at various IEEE and industry conferences. She has held positions of Director at Silicon Valley Engineering Council and TSC chair for Documentation Akraino. She is also a self taught artist who has exhibited at various venues in US and India including University of Illinois Chicago, Life Force Arts Center, Lalit Kala Academy etc.

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08:10 AM – 08:40 AM PDT

Keynote

GROMACS

Erik Lindahl
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Erik Lindahl

Erik Lindahl received a PhD from the KTH Royal Institute of Technology in 2001, and performed postdoctoral research at Groningen University, Stanford University and the Pasteur Institute. He is currently professor of Biophysics at Stockholm University, with a second appointment as professor of Theoretical Biophysics at the Royal Institute of Technology. Lindahl’s research is focused on understanding the molecular mechanisms of membrane proteins, in particular ion channels, through a combination of molecular simulations and experimental work involving cryo-EM and electrophysiology. He has authored some 130 scientific publications and is the recipient of an ERC starting grant.  Lindahl heads the international GROMACS molecular simulation project, which is one of the leading scientific codes to exploit parallelism on all levels from accelerators and assembly code to supercomputers and distributed computing. He is co-director of the Swedish e-Science Research Center as well as the Swedish National Bioinformatics Infrastructure, and lead scientist of the BioExcel Center-of-Excellence for Computational Biomolecular Research. His research work has been awarded with the Prix Jeune Chercheur Blaise Pascal, the Sven and Ebba-Christian Högberg prize, and the Wallenberg Consortium North prize. Lindahl is currently the chair of the PRACE Scientific Steering Committee. 

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08:40 AM -09:20 AM PDT

Tech Talk 1

DPC++ and C/C++/Fortran OpenMP Compilers for CPUs and Xe Accelerators

Xinmin Tian
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Xinmin Tian

Xinmin Tian is a Senior Principal Engineer and Compiler Architect at Intel Corporation and serves as Intel’s representative on OpenMP Architecture Review Board (ARB) and OpenMP C/C++ subcommittee chair. He drives OpenMP offloading, vectorization and parallelization compiler technologies for current and future Intel architectures. His current focus is on DPC++ compiler optimizations for oneAPI Toolkits, LLVM-based OpenMP offloading, and tuning HPC/AI application performance on Intel® CPUs and Xe accelerators. He has a Ph.D. in Computer Science, holds 27 U.S. patents, has published over 60 technical papers with over 1200 citations of his work, and has co-authored three books that span his expertise.

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09:20 AM -10:00 AM PDT

Tech Talk 2

Ginkgo - an Open Source Math Library for the DPC++ Ecosystem

Hartwig Anzt
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Hartwig Anzt

Hartwig Anzt is a research group leader at the Steinbuch Centre for Computing at the Karlsruhe Institute of Technology (KIT). He obtained his PhD in Mathematics at the Karlsruhe Institute of Technology. Afterwards, he joined Jack Dongarra’s Innovative Computing Lab at the University of Tennessee in 2013 until he started his own research group in 2017. He still contributed to the Innovative Computing Lab as a Research Consultant. Hartwig Anzt has a strong background in numerical mathematics, specializes in iterative methods and preconditioning techniques for the next generation hardware architectures. His Helmholtz group on Fixed-point methods for numerics at Exascale (FiNE) is granted funding until 2022. Hartwig Anzt has a long track record of high-quality software development. He is author of the MAGMA-sparse open source software package and managing lead of the Ginkgo numerical linear algebra library. Hartwig Anzt is PI of the EuroHPC project MICROCARD, and a co-PI of the PEEKS project and the xSDK project inside the software technology effort of the US Exascale Computing Project (ECP). He is also the technical PI of the multiprecision effort in the xSDK project, a coordinated effort aiming at integrating low-precision functionality into high-accuracy simulation codes. 

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09:20 AM -10:00 AM PDT

Tech Talk 2

Integrating and Benefits of oneAPI Rendering Toolkit in NCAR VAPOR Climate Visualization App

John Clyne
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John Clyne

John Clyne manages the Visualization and Analysis Systems Technologies (VAST) section at the National Center for Atmospheric Research (NCAR) in Boulder Colorado. VAST is involved in numerous activities related to the visualization and analysis of Earth System Science (ESS) data, including development of open source community software, research, E&O, and production visualization services. John is the chief architect of the widely used VAPOR package. His research interests include volume rendering, flow visualization, and strategies for large, time varying data visualization. He holds an M.S. in computer science from the University of Colorado.

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10:00 AM -10:10 AM PDT Break  
10:10 AM -10:50 AM PDT

Tech Talk 3

Rooflining Bioinformatics: Boosting Epistasis Detection with Cache-aware Roofline Model

Aleksandar Illic
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Aleksandar Ilic

Aleksandar Illic

Aleksandar Ilic (PhD’14) is an Assistant Professor at the Instituto Superior Técnico (IST), Universidade de Lisboa, and a Senior Researcher of INESC-ID, Portugal. He has contributed to more than 50 international journal and conference publications and received several awards for his scientific and teaching achievements, including the HiPEAC 2017 Tech Transfer award for integration of Cache-aware Roofline Model in Intel Advisor. His research interests include high-performance and energy-efficient computing and modeling of parallel heterogeneous systems.

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10:50 AM -11:50 AM PDT

Lightning Talk

OneOligo: Using oneAPI to Accelerate DNA Data Storage

Raja Appuswamy
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Raja Appuswamy

Raja Appuswamy

Raja Appuswamy is an Assistant Professor in the Data Science department at EURECOM–a French Grandes Écoles located in the Sophia Antipolis tech-valley of southern France. Previously, he was as a Researcher and Visiting Professor at EPFL, Switzerland, a Visiting Researcher in the Systems and Networking group at Microsoft Research, Cambridge, and as a Software Development Engineer in the Windows 7 team at Microsoft, Redmond. He received his Ph.D in Computer Science from the Vrije Universiteit, Amsterdam, where he worked under the guidance of Prof. Andrew S. Tanenbaum on designing and implementing a new storage stack for the MINIX 3 microkernel operating system. He also holds dual master’s degrees in computer science and Agricultural Engineering from the University of Florida.

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10:50 AM -11:50 AM PDT

Lightning Talk

HPC Visual Computing and Analysis SW Development at ExaScale

Paul Navratil
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Paul Navratil

Paul A. Navrátil is an expert in high-performance visualization technologies, accelerator-based computing and advanced rendering techniques at the Texas Advanced Computing Center (TACC) at The University of Texas at Austin. His research interests include efficient algorithms for large-scale parallel visualization and data analysis (VDA) and innovative design for large-scale VDA systems. Dr. Navrátil’s recent work includes algorithms for large-scale distributed-memory ray tracing. This work enables photo-realistic rendering of the largest datasets produced on supercomputers today, such as cosmologic simulations of the Universe and computational fluid dynamics simulations at unprecedented levels of detail. He directs the Visualization area at TACC, which includes the Scalable Visualization Technologies (SVT) and Visualization Interfaces and Applications (VIA) groups. Dr. Navrátil’s work has been featured in numerous venues, both nationally and internationally, including the New York Times, Discover, and PBS News Hour. He holds BS, MS and Ph.D. degrees in Computer Science and a BA in Plan II Honors from The University of Texas at Austin.

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11:50 AM -12:10 PM PDT Lunch and Fun Activities  
12:10 PM – 12:50 PM PDT

Tech Talk 4

Extending Rice University’s HPCToolkit to Measure and Analyze the Performance of Applications Accelerated with Intel GPUs

Xiaozhu Meng
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Xiaozhu Meng

Xiaozhu is an active developer for the Rice HPCToolkit. He is presently working on an implementation of the HPCToolkit on top of the Level 0 in oneAPI and have designed and implemented a parallel binary analysis for analyzing program control flow using OpenMP task parallelism and Intel® oneAPI Threading Building Blocks (TBB).

Aaron Cherian
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Aaron Cherian

Aaron Thomas Cherian is a Doctorate Student of Computer Science working under Dr. John Mellor-Crummey at Rice University. He is an active developer for the HPCToolkit project, an integrated suite of tools for measurement and analysis of application performance on computers ranging from desktops to supercomputers. He obtained his Bachelors in Computer Science in 2017 from University of Mumbai, India. His research focuses on the study and instrumentation of binary code and its applications in HPC. He is presently working on implementation of the HPCToolkit on top of the OpenCL API to provide course-grained and fine-grained profile metrics for Intel OpenCL and DPC++ applications.

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12:50 PM – 01:30 PM PDT

Tech Talk 5

Accelerating Oil and Gas Applications with SYCL for FPGAs

Ricardo Menotti
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Ricardo Menotti

Ricardo Menotti holds a doctorate in Computer Science and Computational Mathematics at the University of São Paulo (2010), master’s in computer science and Computational Mathematics at the University of São Paulo (2005) and bachelor’s in computer science from the University of Oeste Paulista (2002). He is currently a professor at the Federal University of São Carlos. He has experience in computer science, with emphasis on computer architecture, reconfigurable computing and compilers.

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01:30 PM – 01:40 PM PDT Break  
01:40 PM – 02:40 PM PDT

Panel

oneAPI Tools Panel

Paul Petersen
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Paul Petersen

Paul Petersen

Paul Petersen is a Sr. Principal Engineer in IAGS (Intel Architecture, Graphics & Software), and oneAPI Tools Architect. He received a Ph.D. in Computer Science from the University of Illinois in 1993. Starting at Kuck and Associates, Inc. (KAI) projects included contributions to the auto-parallelizing compiler (KAP) and was involved in the early definition and implementations of OpenMP. While at KAI, he developed the Assure line of parallelization/correctness products, for Fortran, C++ and Java. In 2000, Intel Corporation acquired KAI, and he joined the software tools group creating the Thread Checker products, which evolved into the Inspector and Advisor components of the Intel® Parallel Studio. Inspector uses dynamic binary instrumentation to detect memory and concurrency bugs, and Advisor uses similar techniques along with performance measurement and modeling to assist developers in transforming existing serial applications to be ready for parallel execution. The focus on product architecture in Parallel Studio XE and its component product architecture transitioned to creating and leading a pathfinding team. The work on defining next generation features for parallel runtimes and software analysis tools to better enable Intel platforms, more recently transitioned to current role leading the oneAPI Tools Architecture team.

Ruyman Reyes
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Ruyman Reyes

Ruyman Reyes

Ruyman is a software engineer with background in High Performance Computing and extensive experience in programming models and heterogeneous platforms. Ruyman holds a PhD from University of La Laguna (Spain). He completed his dissertation, named Directive based approach to Heterogeneous Computing in December 2012, while working as Application Developer in the Edinburgh Parallel Computing Center (EPCC). He moved later in December 2013 to Codeplay Software where he has helped to define the SYCL open standard for heterogeneous programming, led development of ComputeCpp and more recently contributions to the DPC++ compiler project.

Ramesh Peri
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Ramesh Peri

Ramesh Peri

Ramesh is a senior Principal Engineer in IAGS and is the performance architect of oneAPI. His area of expertise includes programming languages, compilers, debuggers, and profilers for Intel datacenter/accelerator/HPC/mobile/IoT platforms. He developed software development tools for number of processors that include machine learning accelerators, DSPs, micro-controllers, GPUs and a variety of application processors based on many different kinds of architectures like x86 and ARM. He holds a Ph.D in computer science from the University of Virginia(USA), an MTech from IIT Kanpur (India), and a BS from REC Warangal (India). Prior to Intel, Ramesh worked at Hewlett Packard, Lucent and Panasonic.

Xiaozhu Meng
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Xiaozhu Meng

Xiaozhu is an active developer for the Rice HPCToolkit. He is presently working on an implementation of the HPCToolkit on top of the Level 0 in oneAPI and have designed and implemented a parallel binary analysis for analyzing program control flow using OpenMP task parallelism and Intel® oneAPI Threading Building Blocks (TBB).

Moderator:

Henry Gabb
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Henry Gabb

Henry A. Gabb is a Senior Principal Engineer in Software and Advanced Technology Group at Intel.  Much of his career has been spent promoting the value of parallel computing, now focusing on oneAPI for heterogeneous parallelism. Henry holds a bachelor’s degree in biochemistry from Louisiana State University, a master’s degree in medical informatics from the Northwestern Feinberg School of Medicine, a doctorate in molecular genetics from the University of Alabama at Birmingham School of Medicine, and a doctorate in information science from the University of Illinois at Urbana-Champaign. Prior to joining Intel, he was Director of Scientific Computing at the US Army Engineer Research and Development Center MSRC, a Department of Defense high-performance computing facility.
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08:00 AM – 8:10 AM PDT

Closing

Closing

Sujata Tibrewala
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Sujata Tibrewala

Sujata Tibrewala is oneAPI Worldwide Developer Community manager at Intel who defines programs to enable developer community to use oneAPI. She is a co-chair for IEEE Edge Automation Platform Roadmap and is a frequent presenter at various IEEE and industry conferences. She has held positions of Director at Silicon Valley Engineering Council and TSC chair for Documentation Akraino. She is also a self taught artist who has exhibited at various venues in US and India including University of Illinois Chicago, Life Force Arts Center, Lalit Kala Academy etc.

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02:50 PM – 03:50 PM PDT

Happy Hour

Virtual Happy Hour and Networking

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Speakers

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Sujata Tibrewala

Sujata Tibrewala is oneAPI Worldwide Developer Community manager at Intel who defines programs to enable developer community to use oneAPI. She is a co-chair for IEEE Edge Automation Platform Roadmap and is a frequent presenter at various IEEE and industry conferences. She has held positions of Director at Silicon Valley Engineering Council and TSC chair for Documentation Akraino. She is also a self taught artist who has exhibited at various venues in US and India including University of Illinois Chicago, Life Force Arts Center, Lalit Kala Academy etc.

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Joseph Curley

Joseph (Joe) Curley serves Intel Corporation as Senior Director, oneAPI Products, Solutions & Ecosystem, SATG. His primary responsibilities include supporting the oneAPI industry initiative, product management of Intel’s oneAPI product implementation, and supporting the oneAPI developer ecosystem. Mr. Curley joined Intel Corporation in 2007, and has served in multiple other strategic planning, ecosystem development, and business leadership roles. Prior to joining Intel, Joe worked at Dell, Inc. leading the global workstation product line, the consumer and small business desktop product line, and in a series of engineering roles. He began his career at computer graphics pioneer Tseng Labs. 

Andrew Richards
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Andrew Richards

Andrew Richards

CEO and co-founder of Codeplay, Andrew started his career writing video games in the days of 8-bit computers, progressing to become a lead games programmer at Eutechnyx™, where he wrote best-selling titles such as Pete Sampras Tennis and Total Drivin’. Codeplay has been producing compilers for games consoles, special-purpose processors and GPUs since then. As well as being CEO and Founder of Codeplay Software Ltd, Andrew is also the Chair of the Software working group of the HSA Foundation™ and former Chair of the SYCL™ for OpenCL™ sub-group of the Khronos® Group. Andrew graduated from Cambridge University with a degree in Computer Science and Physics.

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Ahmed Ayyad

Ahmed is a senior HPC software engineer and a member of Brightskies’ parallel programming team. He works on software benchmarking and code optimization/modernization of the company’s state of the art computational science and numerical analysis products. Ahmed’s work involved developing software optimized for different hardware architectures. Ahmed is part of the Brightskies team that is developing one of the earliest substantial products adopting the oneAPI and DPC++ technologies. Previously Ahmed worked at Valeo, developing automotive software solutions to multiple OEMs. Ahmed holds a B.Sc. in electrical engineering from Alexandria University. He has R&D experience in computer vision, machine learning/deep learning and software architecture.

Denisa Constantinescu
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Denisa Constantinescu

Denisa Constantinescu

Denisa Constantinescu is a Ph.D. student in Mechatronics and a researcher in the Computer Architecture Department at the University of Malaga. She obtained a Master’s degree in Computer Engineering from the University of Malaga in 2017. She was a Research Visitor at the NUCAR Laboratory (Northeastern University, Boston, USA) in 2018. Her research interests are in parallel computing, robotics, intelligent control systems, optimization, and autonomous decision-making.

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Professor Rafael Asenjo

Rafael Asenjo is a Professor of Computer Architecture at the University of Malaga, Spain. He obtained a PhD in Telecommunication Engineering in 1997 and was an Associate Professor at the Computer Architecture Department from 2001 to 2017. He was a Visiting Scholar at the University of Illinois in Urbana-Champaign (UIUC) in 1996 and 1997 and Visiting Research Associate in the same University in 1998. He was also a Research Visitor at IBM T.J. Watson in 2008 and at Cray Inc. in 2011. He has been using TBB since 2008 and over the last five years, he has focused on productively exploiting heterogeneous chips leveraging TBB as the orchestrating framework. In 2013 and 2014 he visited UIUC to work on CPU+GPU chips. In 2015 and 2016 he also started to research into CPU+FPGA chips while visiting U. of Bristol. He served as General Chair for ACM PPoPP’16 and as an Organization Committee member as well as a Program Committee member for several HPC related conferences (PPoPP, SC, PACT, IPDPS, HPCA, EuroPar, and SBAC-PAD). His research interests include heterogeneous programming models and architectures, parallelization of irregular codes and energy consumption. He has co-authored the latest book (open access) on Threading Building Blocks (TBB).

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Attila Krasznahorkay

Attila Krasznahorkay is an Applied Physicist at CERN, having a PhD in Particle Physics. He currently convenes the Accelerator Software Forum of the ATLAS Experiment while working as a core software developer for the experiment, and convenes the Frameworks Working Group of the High Energy Physics Software Foundation (HSF). His work currently focuses on integrating accelerator aided calculations into the ATLAS Experiment’s simulation/reconstruction/analysis software and preparing the ATLAS Experiment’s software for the next data taking period of the Large Hadron Collider.

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Alessandro Faria

Alessandro was born in Bebedouro, state of Sao Paulo, Brazil. He is a speaker, researcher, founder of OITI TECHNOLOGIES. He has worked with technology since 1984, Linux since 1998, biometrics since 1999, facial biometrics since 2003, computer vision since 2005, and GPU since 2009. He is the inventor of CERTIFACE technology, Ambassador openSUSE Linux in Latin America., member OWASP since 2016, member Mozillians since 2017, official contributor OpenCV library since 2017, open source software contributor, and including maintainers librealsense in openSUSE Linux.

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Steffen Christgau

Steffen Christgau is a research associate in the Algorithms for Innovative Architectures research group of the Supercomputing Department at the Zuse Institute Berlin (ZIB). His current research interests are the efficient usage of persistent memory for HPC applications as well as their optimization for new hardware platforms with established and new programming environments. He received his Ph.D. as well as his M.Sc. degree in computer science from the University of Potsdam, Germany. While working at the Operating Systems and Distributed Systems group, his research focused on designing and optimizing MPI implementations for an experimental, non-cache-coherent many-core processor. Before he joined ZIB, he also worked in the industry on compiler implementations and robotic systems as well as a lecturer for parallel computing.

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Marius Knaust

Marius Knaust is a research associate in the Algorithms for Innovative Architectures research group of the Supercomputing Department at the Zuse Institute Berlin (ZIB). His current research interest is the application of FPGAs as HPC compute accelerators and improving the high-level synthesis workflow for it. He received his M.Sc. degree in software engineering from the Hasso Plattner Institute in Potsdam, Germany. Prior to joining ZIB, he worked at the division Microrobotics and Control Engineering of the University of Oldenburg and interned with the Mobile Research group of Yahoo Labs in the Silicon Valley.

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Laura Cappelli

Laura Cappelli is a computer science student at Alma Mater Studiorum – University of Bologna. Her studies span heterogeneous systems and parallel programming models, and her current research focuses on the use of SYCL from the Khronos Group and oneAPI from Intel for performance portability, and their application to physics reconstruction algorithms. In summer 2020, Laura participated to the CERN OpenLab programme, and is now working in collaboration with physicists from the CMS Experiment at CERN. She will defend her master’s thesis on “Performance portability of physics reconstruction algorithms on heterogeneous systems using the SYCL abstraction programming model” in early 2021.

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Ho Leung Ng

Ho Leung Ng is an Associate Professor of Biochemistry & Biophysics at Kansas State University. His primary research interests include protein crystallography, structure-based drug design for cancer and immunology, computational chemistry, applications of machine learning to computational chemistry and drug design, immuno-oncology, protein kinases, estrogen pharmacology, GPCRs, hormone receptors, malaria, fluorescent proteins, and bio photonics. He is the founder of OpenSourceCOVID19 (www.opensourcecovid19.org).

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David Hardy

Dr. David J. Hardy is a Senior Research Programmer at the University of Illinois at Urbana-Champaign. He leads the development of NAMD, an award-winning parallel molecular dynamics code designed for high-performance simulation of large biomolecular systems that, through the use of Charm++ parallel objects, is able to scale to hundreds of thousands of CPU cores and tens of thousands of GPUs. He obtained his PhD in Computer Science in 2006 from the University of Illinois at Urbana-Champaign. His research interests include fast methods for calculating electrostatics, numerical integration methods suitable for Hamiltonian systems, and GPU computing.

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Tareq Malas

Tareq joined Intel after his postdoctoral fellowship in Lawrence Berkeley National Laboratory under the NERSC Exascale Science Applications Program. He obtained his MS and Ph.D. degrees from King Abdullah University of Science and Technology (KAUST), in Saudi Arabia, advised by Prof. David Keyes in the Extreme Computing Research Center. His main areas of research are High Performance Computing in stencil computations and molecular dynamics simulations. He is interested in developing efficient high-performance computing algorithms on contemporary and future architectures for the most demanding applications. He likes to work near the CPU, as he did his Stencil code generation project in performing efficient vectorization in the CPU of the PowerPC 450 processor of the Blue Gene/P supercomputer. He worked on developing novel cache blocking techniques for reducing the data movement in the processor’s memory hierarchy, allowing the use of cache blocks that can efficiency span multiple cache domains. This work was developed in his Girih project for Intel® CPU. He is currently working on the performance optimizations of molecular dynamics simulations.

Gergana Slavova
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Gergana Slavova

Gergana Slavova

Gergana has 14 years’ experience in High Performance Computing (HPC). For the majority of her career, she has focused on customer enabling, training, and consulting for distributed applications using the Message Passing Interface (MPI) and Intel’s development tools. Most recently, she’s participating in the oneAPI industry initiative that works on defining an open cross-vendor, cross-platform programming model for accelerators.

Ronan Keryell
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Ronan Keryell

Ronan Keryell

Ronan Keryell is principal software engineer at Xilinx Research Labs. He works on SYCL C++-based programming models for heterogeneous system like FPGA and CGRA. He is the specification editor of the SYCL standard, member of the SYCL, SPIR & OpenCL standard committees from Khronos Group & ISO C++ committee. Ronan Keryell received his MSc in Electrical Engineering and PhD in Computer Science in 1992 from École Normale Supérieure of Paris & University of Paris Sud (France), on the design of a massively parallel RISC-based VLIW-SIMD graphics computer and its programming environment. He was co-founder of 3 start-ups, mainly in high-performance computing, was the technical lead of the Par4All automatic parallelizer at SILKAN, targeting OpenMP, CUDA & OpenCL from sequential C & Fortran. Before joining Xilinx, he worked at AMD on programming models for GPU.

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Nevin Liber

Nevin Liber is a computer scientist in the ALCF (Argonne Leadership Computing Facility) division of Argonne National Laboratory, where he works on the oneAPI/DPC++/SYCL backend for Kokkos for Aurora. He also represents Argonne on the SYCL and C++ Committees, the latter as Vice Chair of LEWGI/SG18.

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Penporn Koanantakool

Penporn Koanantakool is a senior software engineer at Google. She leads TensorFlow’s performance optimization collaboration with Intel. Penporn holds a Ph.D. in computer science from the University of California, Berkeley, and a B.Eng. in computer engineering from Kasetsart University, Thailand.

Andrew Lumsdaine
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Andrew Lumsdaine

Andrew Lumsdaine

Computing (NIAC), Andrew wears at least two hats: Laboratory Fellow at Pacific Northwest National Laboratory and Affiliate Professor in the Paul G. Allen School of Computer Science and Engineering. As a dual-appointee between UW and PNNL Andrew also has the title of “UW-PNNL Distinguished Faculty Fellow.” By spanning a university and a national laboratory he has the opportunity to work on basic research questions and then reduce those results to practice. His primary research interest is High Performance Computing, interpreted broadly. Of particular interest throughout most of his career has been scalable graph algorithms. He has also had a side interest in computational photography, which turned out to be surprising fruitful.

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Erik Lindahl

Erik Lindahl received a PhD from the KTH Royal Institute of Technology in 2001, and performed postdoctoral research at Groningen University, Stanford University and the Pasteur Institute. He is currently professor of Biophysics at Stockholm University, with a second appointment as professor of Theoretical Biophysics at the Royal Institute of Technology. Lindahl’s research is focused on understanding the molecular mechanisms of membrane proteins, in particular ion channels, through a combination of molecular simulations and experimental work involving cryo-EM and electrophysiology. He has authored some 130 scientific publications and is the recipient of an ERC starting grant.  Lindahl heads the international GROMACS molecular simulation project, which is one of the leading scientific codes to exploit parallelism on all levels from accelerators and assembly code to supercomputers and distributed computing. He is co-director of the Swedish e-Science Research Center as well as the Swedish National Bioinformatics Infrastructure, and lead scientist of the BioExcel Center-of-Excellence for Computational Biomolecular Research. His research work has been awarded with the Prix Jeune Chercheur Blaise Pascal, the Sven and Ebba-Christian Högberg prize, and the Wallenberg Consortium North prize. Lindahl is currently the chair of the PRACE Scientific Steering Committee. 

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Xinmin Tian

Xinmin Tian is a Senior Principal Engineer and Compiler Architect at Intel Corporation and serves as Intel’s representative on OpenMP Architecture Review Board (ARB) and OpenMP C/C++ subcommittee chair. He drives OpenMP offloading, vectorization and parallelization compiler technologies for current and future Intel architectures. His current focus is on DPC++ compiler optimizations for oneAPI Toolkits, LLVM-based OpenMP offloading, and tuning HPC/AI application performance on Intel® CPUs and Xe accelerators. He has a Ph.D. in Computer Science, holds 27 U.S. patents, has published over 60 technical papers with over 1200 citations of his work, and has co-authored three books that span his expertise.

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Hartwig Anzt

Hartwig Anzt is a research group leader at the Steinbuch Centre for Computing at the Karlsruhe Institute of Technology (KIT). He obtained his PhD in Mathematics at the Karlsruhe Institute of Technology. Afterwards, he joined Jack Dongarra’s Innovative Computing Lab at the University of Tennessee in 2013 until he started his own research group in 2017. He still contributed to the Innovative Computing Lab as a Research Consultant. Hartwig Anzt has a strong background in numerical mathematics, specializes in iterative methods and preconditioning techniques for the next generation hardware architectures. His Helmholtz group on Fixed-point methods for numerics at Exascale (FiNE) is granted funding until 2022. Hartwig Anzt has a long track record of high-quality software development. He is author of the MAGMA-sparse open source software package and managing lead of the Ginkgo numerical linear algebra library. Hartwig Anzt is PI of the EuroHPC project MICROCARD, and a co-PI of the PEEKS project and the xSDK project inside the software technology effort of the US Exascale Computing Project (ECP). He is also the technical PI of the multiprecision effort in the xSDK project, a coordinated effort aiming at integrating low-precision functionality into high-accuracy simulation codes. 

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John Clyne

John Clyne manages the Visualization and Analysis Systems Technologies (VAST) section at the National Center for Atmospheric Research (NCAR) in Boulder Colorado. VAST is involved in numerous activities related to the visualization and analysis of Earth System Science (ESS) data, including development of open source community software, research, E&O, and production visualization services. John is the chief architect of the widely used VAPOR package. His research interests include volume rendering, flow visualization, and strategies for large, time varying data visualization. He holds an M.S. in computer science from the University of Colorado.

Aleksandar Ilic
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Aleksandar Ilic

Aleksandar Illic

Aleksandar Ilic (PhD’14) is an Assistant Professor at the Instituto Superior Técnico (IST), Universidade de Lisboa, and a Senior Researcher of INESC-ID, Portugal. He has contributed to more than 50 international journal and conference publications and received several awards for his scientific and teaching achievements, including the HiPEAC 2017 Tech Transfer award for integration of Cache-aware Roofline Model in Intel Advisor. His research interests include high-performance and energy-efficient computing and modeling of parallel heterogeneous systems.

Raja Appuswamy
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Raja Appuswamy

Raja Appuswamy

Raja Appuswamy is an Assistant Professor in the Data Science department at EURECOM–a French Grandes Écoles located in the Sophia Antipolis tech-valley of southern France. Previously, he was as a Researcher and Visiting Professor at EPFL, Switzerland, a Visiting Researcher in the Systems and Networking group at Microsoft Research, Cambridge, and as a Software Development Engineer in the Windows 7 team at Microsoft, Redmond. He received his Ph.D in Computer Science from the Vrije Universiteit, Amsterdam, where he worked under the guidance of Prof. Andrew S. Tanenbaum on designing and implementing a new storage stack for the MINIX 3 microkernel operating system. He also holds dual master’s degrees in computer science and Agricultural Engineering from the University of Florida.

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Paul Navratil

Paul A. Navrátil is an expert in high-performance visualization technologies, accelerator-based computing and advanced rendering techniques at the Texas Advanced Computing Center (TACC) at The University of Texas at Austin. His research interests include efficient algorithms for large-scale parallel visualization and data analysis (VDA) and innovative design for large-scale VDA systems. Dr. Navrátil’s recent work includes algorithms for large-scale distributed-memory ray tracing. This work enables photo-realistic rendering of the largest datasets produced on supercomputers today, such as cosmologic simulations of the Universe and computational fluid dynamics simulations at unprecedented levels of detail. He directs the Visualization area at TACC, which includes the Scalable Visualization Technologies (SVT) and Visualization Interfaces and Applications (VIA) groups. Dr. Navrátil’s work has been featured in numerous venues, both nationally and internationally, including the New York Times, Discover, and PBS News Hour. He holds BS, MS and Ph.D. degrees in Computer Science and a BA in Plan II Honors from The University of Texas at Austin.

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Xiaozhu Meng

Xiaozhu is an active developer for the Rice HPCToolkit. He is presently working on an implementation of the HPCToolkit on top of the Level 0 in oneAPI and have designed and implemented a parallel binary analysis for analyzing program control flow using OpenMP task parallelism and Intel® oneAPI Threading Building Blocks (TBB).

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Aaron Cherian

Aaron Thomas Cherian is a Doctorate Student of Computer Science working under Dr. John Mellor-Crummey at Rice University. He is an active developer for the HPCToolkit project, an integrated suite of tools for measurement and analysis of application performance on computers ranging from desktops to supercomputers. He obtained his Bachelors in Computer Science in 2017 from University of Mumbai, India. His research focuses on the study and instrumentation of binary code and its applications in HPC. He is presently working on implementation of the HPCToolkit on top of the OpenCL API to provide course-grained and fine-grained profile metrics for Intel OpenCL and DPC++ applications.

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Ricardo Menotti

Ricardo Menotti holds a doctorate in Computer Science and Computational Mathematics at the University of São Paulo (2010), master’s in computer science and Computational Mathematics at the University of São Paulo (2005) and bachelor’s in computer science from the University of Oeste Paulista (2002). He is currently a professor at the Federal University of São Carlos. He has experience in computer science, with emphasis on computer architecture, reconfigurable computing and compilers.

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Henry Gabb

Henry A. Gabb is a Senior Principal Engineer in Software and Advanced Technology Group at Intel.  Much of his career has been spent promoting the value of parallel computing, now focusing on oneAPI for heterogeneous parallelism. Henry holds a bachelor’s degree in biochemistry from Louisiana State University, a master’s degree in medical informatics from the Northwestern Feinberg School of Medicine, a doctorate in molecular genetics from the University of Alabama at Birmingham School of Medicine, and a doctorate in information science from the University of Illinois at Urbana-Champaign. Prior to joining Intel, he was Director of Scientific Computing at the US Army Engineer Research and Development Center MSRC, a Department of Defense high-performance computing facility.
Paul Petersen
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Paul Petersen

Paul Petersen

Paul Petersen is a Sr. Principal Engineer in IAGS (Intel Architecture, Graphics & Software), and oneAPI Tools Architect. He received a Ph.D. in Computer Science from the University of Illinois in 1993. Starting at Kuck and Associates, Inc. (KAI) projects included contributions to the auto-parallelizing compiler (KAP) and was involved in the early definition and implementations of OpenMP. While at KAI, he developed the Assure line of parallelization/correctness products, for Fortran, C++ and Java. In 2000, Intel Corporation acquired KAI, and he joined the software tools group creating the Thread Checker products, which evolved into the Inspector and Advisor components of the Intel® Parallel Studio. Inspector uses dynamic binary instrumentation to detect memory and concurrency bugs, and Advisor uses similar techniques along with performance measurement and modeling to assist developers in transforming existing serial applications to be ready for parallel execution. The focus on product architecture in Parallel Studio XE and its component product architecture transitioned to creating and leading a pathfinding team. The work on defining next generation features for parallel runtimes and software analysis tools to better enable Intel platforms, more recently transitioned to current role leading the oneAPI Tools Architecture team.

Ruyman Reyes
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Ruyman Reyes

Ruyman Reyes

Ruyman is a software engineer with background in High Performance Computing and extensive experience in programming models and heterogeneous platforms. Ruyman holds a PhD from University of La Laguna (Spain). He completed his dissertation, named Directive based approach to Heterogeneous Computing in December 2012, while working as Application Developer in the Edinburgh Parallel Computing Center (EPCC). He moved later in December 2013 to Codeplay Software where he has helped to define the SYCL open standard for heterogeneous programming, led development of ComputeCpp and more recently contributions to the DPC++ compiler project.

Ramesh Peri
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Ramesh Peri

Ramesh Peri

Ramesh is a senior Principal Engineer in IAGS and is the performance architect of oneAPI. His area of expertise includes programming languages, compilers, debuggers, and profilers for Intel datacenter/accelerator/HPC/mobile/IoT platforms. He developed software development tools for number of processors that include machine learning accelerators, DSPs, micro-controllers, GPUs and a variety of application processors based on many different kinds of architectures like x86 and ARM. He holds a Ph.D in computer science from the University of Virginia(USA), an MTech from IIT Kanpur (India), and a BS from REC Warangal (India). Prior to Intel, Ramesh worked at Hewlett Packard, Lucent and Panasonic.

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