10:00 - 10:10 CET
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Introduction
Sujata Tibrewala,
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Sujata Tibrewala
Sujata Tibrewala is oneAPI Worldwide Developer Community manager at Intel who defines programs to enable developer community to use oneAPI. She is a co-chair for IEEE Edge Automation Platform Roadmap and is a frequent presenter at various IEEE and industry conferences. She has held positions of Director at Silicon Valley Engineering Council and TSC chair for Documentation Akraino. She is also a self taught artist who has exhibited at various venues in US and India including University of Illinois Chicago, Life Force Arts Center, Lalit Kala Academy etc.
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10:10 – 10:50 AM CET
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Experiences with adding SYCL support to GROMACS
Erik Lindahl,
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Erik Lindahl
Erik Lindahl received a PhD from the KTH Royal Institute of Technology in 2001, and performed postdoctoral research at Groningen University, Stanford University and the Pasteur Institute. He is currently professor of Biophysics at Stockholm University, with a second appointment as professor of Theoretical Biophysics at the Royal Institute of Technology. Lindahl’s research is focused on understanding the molecular mechanisms of membrane proteins, in particular ion channels, through a combination of molecular simulations and experimental work involving cryo-EM and electrophysiology. He has authored some 130 scientific publications and is the recipient of an ERC starting grant. Lindahl heads the international GROMACS molecular simulation project, which is one of the leading scientific codes to exploit parallelism on all levels from accelerators and assembly code to supercomputers and distributed computing. He is co-director of the Swedish e-Science Research Center as well as the Swedish National Bioinformatics Infrastructure, and lead scientist of the BioExcel Center-of-Excellence for Computational Biomolecular Research. His research work has been awarded with the Prix Jeune Chercheur Blaise Pascal, the Sven and Ebba-Christian Högberg prize, and the Wallenberg Consortium North prize. Lindahl is currently the chair of the PRACE Scientific Steering Committee.
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10:50 - 11:20 CET
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AdePT project - Experience with porting particle transport simulation to oneAPI
Daniel-Florin Dosaru,
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Daniel-Florin Dosaru
I am a master’s student in Computer Science at EPFL, and I am working on my master thesis as a Technical Student CERN in EP/SFT group. I would describe myself as a computer systems enthusiast, passionate about parallel programming, networking, and security.
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11:20 - 11:30 CET |
BREAK |
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11:30 - 1:00 CET
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Single source heterogeneous programming with Data Parallel C++ and SYCL 2020 features
Rakshith Krishnappa,
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Rakshith Krishnappa
Rakshith is a developer evangelist at Intel, focused on oneAPI, DPC++ and High Performance Computing. For the last 16 years he has worked on various Intel products including CPUs, GPUs, HPC products and Software solutions.
Praveen Kundurthy,
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Praveen Kundurthy
Praveen Kundurthy is a Developer Evangelist at Intel with over 15 years of experience in software development and optimization on Intel platforms. In his current role, he works with universities and developers to help them learn and utilize oneAPI for their projects. He has expertise in C++, C#, and Python programing languages. Over the past few years at Intel, he has worked on topics spanning artificial intelligence, storage technologies, gaming, virtual reality and Android. Praveen has a Master’s Degree in Computer Engineering from Mississippi State University.
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1:00 - 1:20 CET |
LUNCH |
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1:20 - 2:50 CET
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Porting NAMD to oneAPI DPC++
Jaemin Choi,
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Jaemin Choi
Jaemin Choi is a PhD candidate in Computer Science at the University of Illinois at Urbana-Champaign. His research is focused on efficient execution of asynchronous task-based programming models such as Charm++ on GPU-accelerated systems.
David Hardy,
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David Hardy
David Hardy is a senior research programmer at the University of Illinois at Urbana-Champaign. He leads the development of NAMD and was part of the research effort awarded in 2020 the ACM Gordon Bell Special Prize for High Performance Computing-Based COVID-19 Research.
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2:50 - 3:00 CET |
BREAK |
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3:00 - 3:40 CET
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Experiences in Using oneAPI
Tom Deakin,
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Tom Deakin
Dr Tom Deakin is a Senior Research Associate in the High Performance Computing Research Group at the University of Bristol. His research interests include performance portability. Tom is the Chair of the Khronos SYCL Advisory Panel and member of the SYCL Working Group. More at hpc.tomdeakin.com.
Micheal Wong,
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Micheal Wong
Micheal Wong is the Vice President of Research and Development at Codeplay Software, a Scottish company that produces compilers, debuggers, runtimes, testing systems, and other specialized tools to aid software development for heterogeneous systems, accelerators and special purpose processor architectures, including GPUs and DSPs. He is now a member of the open consortium group known as Khronos, MISRA, and AUTOSAR and is Chair of the Khronos C++ Heterogeneous Programming language SYCL, used for GPU dispatch in native modern C++ (14/17), OpenCL, as well as guiding the research and development teams of ComputeSuite, ComputeAorta/ComputeCPP. For twenty years, he was the Senior Technical Strategy Architect for IBM compilers.
Aksel Alpay,
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Aksel Alpay
Aksel Alpay is a researcher and software engineer from Heidelberg University, where he works on high performance computing topics. In particular, he is the creator and lead developer of the hipSYCL SYCL implementation, and also engages within the Khronos SYCL working group to advance the language.
James Reinders,
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James Reinders
James Reinders is a senior engineer who joined Intel Corporation in 1989 and has contributed to projects including systolic arrays systems WARP and iWarp, and the world’s first TeraFLOP supercomputer (ASCI Red), as well as compilers and architecture work for multiple Intel processors and parallel systems. James has been a driver behind the development of Intel as a major provider of software development products, and serves as their chief software evangelist. His most recent book is Data Parallel C++, Mastering DPC++ for Programming of Heterogeneous Systems using C++ and SYCL.
Kris Rowe,
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Kris Rowe
Kris is an Assistant Computational Scientist in the Performance Engineering Group at Argonne National Laboratory’s Leadership Computing Facility. He holds a PhD in applied mathematics from the University of Waterloo.
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3:40 - 4:10 CET
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Evaluating CUDA Portability with HIPCL and DPCT
Zheming Jin,
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Zheming Jin
I finished my Ph.D. in Computer Science and Engineering at University of South Carolina, where my research focused on program synthesis and applications development targeting FPGAs. As a postdoctoral appointee at Argonne, I evaluated high-level synthesis and oneAPI on FPGAs and GPUs, respectively. My research focus is heterogeneous computing.
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4:10 - 4:40 CET
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Design, Development and Validation of DPC++ backend for OCCA
Anoop Madhusoodhanan Prabha ,
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Anoop Madhusoodhanan Prabha
Anoop is a Senior Technical Consulting Engineer at Intel specializing in Heterogeneous computing and code modernization. He holds a MS in Electrical Engineering from State University of New York at Buffalo.
Cedric Andreolli,
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Cedric Andreolli
Cedric is an Application Engineer working on codesign projects at Intel. His expertise includes optimization of HPC workloads as well as application characterization. He holds a master’s degree in Computer Science from INSA in France.
Saumil Sudhir Patel,
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Saumil Sudhir Patel
Saumil is an Assistant Computational Scientist in the Computational Science Division at Argonne National Laboratory. He holds a PhD in Mechanical Engineering from The City College of New York.
Kris Rowe,
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Kris Rowe
Kris is an Assistant Computational Scientist in the Performance Engineering Group at Argonne National Laboratory’s Leadership Computing Facility. He holds a PhD in applied mathematics from the University of Waterloo.
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4:40 – 5:10 AM CET
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Porting oneAPI DPC++ on Xilinx FPGA & Versal ACAP CGRA
Ronan Keryell,
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Ronan Keryell
Ronan Keryell is principal software engineer at Xilinx Research Labs. He works on SYCL C++-based programming models for heterogeneous system like FPGA and CGRA. He is the specification editor of the SYCL standard, member of the SYCL, SPIR & OpenCL standard committees from Khronos Group & ISO C++ committee. Ronan Keryell received his MSc in Electrical Engineering and PhD in Computer Science in 1992 from École Normale Supérieure of Paris & University of Paris Sud (France), on the design of a massively parallel RISC-based VLIW-SIMD graphics computer and its programming environment.
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5:10 - 5:20 CET |
BREAK |
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5:20 - 5:50 CET
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TensorFlow and oneDNN in Partnership
Penporn Koanantakool,
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Penporn Koanantakool
Penporn Koanantakool is a senior software engineer at Google. She leads TensorFlow’s performance optimization collaboration with Intel. Penporn holds a Ph.D. in computer science from the University of California, Berkeley, and a B.Eng. in computer engineering from Kasetsart University, Thailand.
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5:50 - 6:00 CET
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Conclusion
Sujata Tibrewala,
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Sujata Tibrewala
Sujata Tibrewala is oneAPI Worldwide Developer Community manager at Intel who defines programs to enable developer community to use oneAPI. She is a co-chair for IEEE Edge Automation Platform Roadmap and is a frequent presenter at various IEEE and industry conferences. She has held positions of Director at Silicon Valley Engineering Council and TSC chair for Documentation Akraino. She is also a self taught artist who has exhibited at various venues in US and India including University of Illinois Chicago, Life Force Arts Center, Lalit Kala Academy etc.
Pranati Tewari,
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Pranati Tewari
Pranati Tewari joined Intel in 2011. She is a Product Marketing Engineer for Intel® oneAPI Priority Support. She assists customers and sales channel with information on product configuration, SKUs, pricing, and support. She is also responsible for product marketing of Intel® Graphics Performance Analyzers (Intel® GPA) and game development tools.
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6:00 - 7:00 PM CET
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Happy Hour
Sujata Tibrewala,
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Sujata Tibrewala
Sujata Tibrewala is oneAPI Worldwide Developer Community manager at Intel who defines programs to enable developer community to use oneAPI. She is a co-chair for IEEE Edge Automation Platform Roadmap and is a frequent presenter at various IEEE and industry conferences. She has held positions of Director at Silicon Valley Engineering Council and TSC chair for Documentation Akraino. She is also a self taught artist who has exhibited at various venues in US and India including University of Illinois Chicago, Life Force Arts Center, Lalit Kala Academy etc.
Russ Beutler,
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Russ Beutler
Russ Beutler is an Engagement Manager for oneAPI in the Developer Ecosystem Programs Team in the Intel Architecture Graphics and Software group. Previously he was the marketing manager for Intel® persistent memory and moderncode developer programs. He has over twenty-five years’ worldwide hardware and software marketing, consulting, and IT experience – twenty-one of which are at Intel.
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