Spatial DPC++ constructs for algorithm acceleration with FPGAs

Field programmable gate arrays (FPGAs) have gained increasing mindshare as an architecture through which workloads can be accelerated in a power-efficient way, particularly when existing accelerators aren’t tuned for or well matched with a workload of interest. They allow a custom architecture to be built for the algorithm of interest without resorting to costly ASIC design, and therefore bridge a gap in performance between a flexible ISA architecture that isn’t quite the right fit for performance, and a custom ASIC designed for the workload.
As a reconfigurable spatial architecture, FPGAs allow implementation of algorithms in a fundamentally different way from instruction set architecture (ISA) accelerators. They can be thought of as implementing an algorithm at the same level of abstraction as an ISA machine would itself be designed and constructed. To enable productivity compared with conventional chip design languages and tools, high level languages including SYCL (and DPC++ which extends SYCL) have been made available to program FPGAs.
This talk will overview the most significant language features on top of SYCL that simplify expression of spatial constructs, and the resultant mapping of these constructs to a device will be depicted. Specifically, parallel execution of kernels with pairwise independent forward progress will be described, as will the variety of communication mechanisms enabled by the pipes features. Memory system tuning controls will be overviewed, and the recommended report-driven methodology for development will be described.

The audience will leave this talk with an overview of spatial language constructs exposed in SYCL and DPC++ , and how to reason about them. Attendance will make it easier to get started adapting algorithms for spatial accelerator implementation, both in terms of initial implementation and also optimization.


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